Further the bridges are processed to standard VLSI place and route. The performance is evaluated and compared. Bridges such as two flip flop and locally delayed latching are designed and implemented. Each clock is separately applied for Wishbone Master and Wishbone Slave thus acts as two as different clock domain systems w.r.t signals that are propagated between them. In this project, the bridges are applied to the Wishbone bus in which two clocks differs from each other, in frequency and phase. 62/926,255 titled Multi-Reset and Multi-Clock Synchronizer, and Synchronous Multi- Cycle Reset Synchronization Circuit filed October 25, 2019, which is incorporated by reference in its. Synchronization bridge is required in between multiple clock domains to avoid the risk of metastability to those signals which are prone to frequent transitions, and are propagated between two multiple clock domains. What are different ways to synchronize between two clock domains Synchronizer techniques for multi-clock domain SoCs & FPGAs. The performance of clock synchronization directly determines the comprehensive performance of distributed cooperative systems such as multi-base radar detection and smart grid. In GALS clock system each block/island is locally synchronous and connected to other blocks by an asynchronous interconnect system. Clock synchronization is the basic service of information communication and the related research has been in the ascendant. One way to overcome this difficulty is to employ GALS clock system. Systems with embedded processors generally requires high speed clocks, it becomes very difficult to maintain one global clock connected all sub blocks to meet the speed requirement of the system. Modern SoC employ multi clock domains on the same die, this is because each block of the system may require different clock voltage and frequencies which results to economical benefits. Evaluation of synchronization methods in multi-clock domain systems

Multiclock domain synchronization